What project owners need to know.
Polysilicon consumption per watt (g/W) is the mass of polysilicon needed to make one watt of solar cell capacity. The ITRPV 2026 roadmap puts TOPCon at about 1.84 g/W for G12 wafers, 1.68 g/W for M10 and 1.61 g/W for G12R, falling to roughly 1.27–1.39 g/W by 2036 through thinner wafers, less cutting loss and higher cell efficiency.
What g/W measures
Grams per watt links the top of the value chain to the bottom. It counts all the polysilicon that goes into a cell's wafer, including the silicon lost when the ingot is squared, cropped and sliced, and divides it by the cell's rated power. A lower number means less polysilicon has to be refined, melted and pulled for every gigawatt of modules.
Because polysilicon refining is energy-intensive and, for India, almost entirely imported, g/W is a useful lens for both cost exposure and supply security. It is a technology metric, not a price: the same g/W can carry very different costs depending on the polysilicon market.
The ITRPV 2026 numbers
The International Technology Roadmap for Photovoltaic (ITRPV), published by VDMA and released at Intersolar Europe in June 2026, gives polysilicon consumption for TOPCon by wafer format. TaiyangNews reported the values as 1.84 g/W for G12, 1.61 g/W for G12R and 1.68 g/W for M10 in 2026, falling to 1.39, 1.29 and 1.27 g/W respectively by 2036.
PV Tech, reporting the same edition, described the ten-year reduction in polysilicon use per wafer as about 26 percent. Different articles use slightly different baselines, so quote the format and year together and treat the figures as roadmap estimates rather than measured plant values.
- G12: 1.84 g/W (2026) → 1.39 g/W (2036)
- G12R: 1.61 g/W (2026) → 1.29 g/W (2036)
- M10: 1.68 g/W (2026) → 1.27 g/W (2036)
Four levers that push g/W down
Wafer thickness is the most visible lever. ITRPV 2026 cites TOPCon wafers at about 130 µm, trending towards about 120 µm by 2036, with heterojunction wafers thinner still. Thinner wafers only help if breakage stays under control in slicing, cell processing and module assembly.
Kerf loss is the silicon turned into sawing sludge. Finer diamond wire narrows each cut, so more wafers come from the same ingot length. Ingot yield is the share of the polysilicon charge that ends up as usable, dislocation-free crystal after crown, tail and side slabs are removed; better hot-zone control and crucible quality help here. Cell efficiency is the fourth lever: more watts from the same wafer lowers g/W even if the wafer itself is unchanged.
- Thinner wafers, with breakage controlled
- Narrower kerf from finer diamond wire
- Higher Czochralski ingot yield
- Higher cell efficiency per wafer
Why it matters for India
A NITI Aayog report produced with Crisil, covered by Down To Earth in 2025, put India's import dependence at about 100 percent for polysilicon and more than 90 percent for wafers, even as module capacity passed 100 GW. Every reduction in g/W lowers the volume of polysilicon the country has to source for the same deployment.
It also changes upstream planning. When ALMM List-III brings ingots and wafers under the domestic-manufacturing framework from 1 June 2028, ingot makers will compete on yield and wafer makers on thickness and kerf. Those are process-control questions as much as equipment questions.
An illustrative calculation
Clearly labelled as an illustration, not a plant figure: at 1.68 g/W, a 1 GW TOPCon programme on M10 wafers implies roughly 1.68 million kilograms, or about 1,680 tonnes, of polysilicon. At the 2036 projection of 1.27 g/W, the same gigawatt would need about 1,270 tonnes. Real plant consumption depends on its own yields, wafer thickness and cell efficiency.
How JRST supports this requirement
JRST works on the parts of the chain where g/W is decided upstream: Czochralski ingot growth, quartz crucibles and high-purity quartz sand, with Maharashtra's first silicon-ingot line in Nagpur. We help project teams think about yield and material quality alongside equipment. This guide summarises public roadmap figures as of the date shown. They are industry estimates and can change; confirm against the current ITRPV edition before using them in a procurement or investment decision.
Discuss your requirement
Mohammed Saif Zaveri connects JRST's industrial content to execution conversations.
As Co-Founder and designated partner of JRST Technology LLP, Mohammed Saif Zaveri works across industrial growth, strategic partnerships, client conversations, equipment strategy, and project pathways for silicon, solar, semiconductor, and advanced-manufacturing opportunities.
This knowledge page is part of JRST's public industrial knowledge base, designed to help buyers move from search terms and early research toward a structured technical-commercial discussion.
View Mohammed Saif Zaveri's profileConnect on LinkedInFrequently asked questions
How many grams of polysilicon per watt does a TOPCon cell use?
The ITRPV 2026 roadmap puts TOPCon at about 1.84 g/W for G12 wafers, 1.68 g/W for M10 and 1.61 g/W for G12R in 2026.
Will polysilicon use per watt keep falling?
ITRPV projects TOPCon falling to roughly 1.27–1.39 g/W by 2036, driven by thinner wafers, narrower kerf and higher efficiency.
Does a thinner wafer always reduce polysilicon use?
Only if breakage and kerf stay under control. A thinner wafer that breaks more often in slicing or cell processing can cancel out the saving.
What is Czochralski ingot yield?
The share of the polysilicon charge that becomes usable, dislocation-free crystal after the crown, tail and side slabs are removed.
Why does g/W matter for India?
India imports almost all of its polysilicon, according to a NITI Aayog report. Lower g/W means less polysilicon has to be sourced for every gigawatt of solar.
Primary sources and further reading
Last reviewed 2026-10-20. Technical scope, policy eligibility, availability, and commercial terms should be independently confirmed for each project.