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N-Type Transition

The N-Type and TOPCon Transition: What It Means for Indian Wafer Projects

Why the solar industry has shifted from p-type PERC to n-type TOPCon, what that changes at the ingot and wafer level, and how Indian wafer projects should specify for it.

Direct answer

What project owners need to know.

The global solar industry has moved its base material from p-type to n-type silicon. N-type tunnel oxide passivated contact (TOPCon) cells overtook p-type PERC in market share during 2024, and ITRPV's 2026 edition puts n-type wafers at roughly 82% of production in 2025, projecting more than 98% within ten years. For an Indian ingot or wafer project, this is not a downstream cell-maker's problem. N-type changes the dopant, the resistivity control problem, the purity and lifetime targets, the thickness the wafer has to survive, and therefore the equipment, consumables and metrology a plant needs to specify before it orders anything.

~82%N-type share of wafer production, 2025
More than 98%Projected n-type share within ten years
110 µmProjected G12 IBC wafer thickness
01

What actually changed, and how fast

The transition happened faster than most capacity plans assumed. N-type TOPCon surpassed p-type PERC in market share during 2024, and by 2025 n-type wafers accounted for approximately 82% of production according to ITRPV's 2026 edition, which projects that share rising above 98% within its ten-year horizon. Coverage of the same roadmap reports p-type falling below 5% share by 2035 and laser-enhanced contact optimisation now close to fully adopted on TOPCon lines.

Format moved at the same time. M6 has effectively disappeared from the market, and larger formats — G12 and the rectangular G12R — now hold the largest share and are expected to keep it. Thickness is moving with them: p-type as-cut thickness has broadly stabilised near 130 µm while n-type continues down toward 120 µm, with G12 IBC wafers projected to reach 110 µm within the roadmap period.

The practical consequence for anyone specifying an ingot or wafer line today is that the p-type reference case is a historical one. A plant designed around legacy P-type formats and thicknesses is being built for a market segment that the published roadmap expects to be residual within a decade.

  • Treat n-type as the default product assumption, not an upgrade path to decide later
  • Specify format capability around G12 and G12R rather than legacy formats
  • Assume as-cut thickness will step down during the plant's life, and buy headroom for it
02

Why the industry moved: the material case

The shift is driven by the physics of the substrate, not by fashion. Peer-reviewed work on n-type base crystalline silicon identifies two structural advantages. First, phosphorus-doped n-type material contains no boron, so the boron-oxygen complexes responsible for light-induced degradation are eliminated even at higher oxygen concentrations. Second, n-type silicon is markedly more tolerant of the metallic impurities that matter most in practice — interstitial iron in particular is far more damaging in p-type material — and n-type substrates offer higher minority-carrier diffusion lengths than p-type substrates at comparable impurity levels.

Those two properties compound. Better tolerance of contamination means a given feedstock and hot-zone environment yields usable material more reliably, and the absence of a degradation mechanism means the cell's rated performance is more durable in the field. That is why the higher-efficiency cell architectures — TOPCon, heterojunction and back-contact variants — have all converged on an n-type base.

Silicon intensity is falling alongside the transition. ITRPV's 2026 edition projects polysilicon consumption per watt declining across formats over the decade, reaching approximately 1.27 g/W for M10 and 1.39 g/W for G12 by 2036, driven by thinner wafers and better yields. For upstream planning, the direction is unambiguous: each watt of downstream demand consumes progressively less silicon, and the wafer has to get thinner to deliver that.

  • Understand n-type's advantage as impurity tolerance and absence of B-O degradation, not simply higher efficiency
  • Expect purity and contamination discipline to carry more commercial weight than in a p-type plant
  • Plan for declining silicon intensity per watt rather than a fixed feedstock-to-output ratio
03

What n-type means at the ingot and wafer level

The most consequential difference in the crystal-growth step is dopant behaviour. Published work on n-type silicon notes that phosphorus has a segregation coefficient of about 0.35 against roughly 0.7 for boron, which produces greater resistivity variation along the length of an n-type ingot and reduces the fraction of the crystal that falls inside a customer's resistivity window. A plant converting from p-type thinking will find that axial resistivity uniformity, not growth speed, is what constrains sellable output.

Purity control tightens in parallel. Because n-type cells are qualified on bulk lifetime, the interstitial oxygen and carbon carried in from feedstock, crucible and hot zone become acceptance-relevant rather than nuisance parameters. That pushes the specification back into quartz crucible grade, graphite hot-zone purity, argon and vacuum integrity, and feedstock quality — the parts of the plant that are easy to under-specify because they do not look like the machine.

Downstream, thinner n-type wafers meet a slicing process that gets harder with every micron removed. Published research on fixed diamond-wire sawing found breakage rising sharply as wafers thin, with the deepest part of the cut the highest-risk phase. A line qualified comfortably at one thickness can lose yield at the next step down without any obvious change in setup, which is why thickness headroom belongs in the equipment specification rather than in a later upgrade discussion.

None of this makes n-type harder in an absolute sense. It makes the plant's quality system, not its nameplate capacity, the thing that determines whether output is sellable.

  • Make axial resistivity control and the resulting usable-ingot fraction an explicit design and acceptance topic
  • Push oxygen, carbon and metallic contamination limits back into crucible, hot-zone, gas and feedstock specifications
  • Define bulk-lifetime and resistivity measurement capability as part of the line, not as an optional add-on
  • Confirm with suppliers how a proposed configuration behaves at the next thickness step down, supported by evidence
04

Planning an Indian wafer project against an n-type market

India's downstream mix is still in transition, which creates a genuine specification question rather than an obvious answer. Reporting on the current ALMM List-II position in July 2026 put total enlisted solar cell capacity at around 30.98 GW across 15 manufacturers, with mono PERC still the largest single block at roughly 16.06 GW — about 52% — and TOPCon at roughly a third of approved capacity. So a domestic wafer producer faces near-term customers running both technologies, against a global roadmap where one of them is disappearing.

The upstream policy signal is much clearer. MNRE has extended the ALMM framework to ingots and wafers with effect from 1 June 2028, and a manufacturer seeking wafer enlistment must hold equivalent ingot capacity. Speaking at a Confederation of Indian Industry event in New Delhi on 7 August 2026, MNRE Secretary Santosh Kumar Sarangi said India is targeting at least 80 GW of domestic ingot and wafer capacity by June 2028, against roughly 33 GW of operating cell capacity at the time, and set out a proposed PLI scheme covering more than 10 GW of polysilicon capacity — a segment where India currently relies substantially on imports.

Read together, the sensible planning posture is to specify for n-type as the base case while retaining the ability to serve p-type demand during the crossover, and to make that decision explicitly rather than by default. The choice cascades: dopant handling, resistivity acceptance windows, purity limits, hot-zone and crucible grades, slicing thickness headroom, and the metrology evidence a customer or an enlistment process may ask to see. It also determines what the feedstock contract has to guarantee, since n-type qualification is only as good as the polysilicon behind it.

Commercial evaluation of any specific configuration is project-specific and should be assessed against a defined product, output and customer route rather than against general industry figures. Every figure in this guide is drawn from public technical, market and policy sources and should be validated against current official documents, supplier specifications and independent professional advice before capital is committed. JRST can support that validation work where it is useful.

  • Decide the n-type/p-type product position deliberately and write it into the specification, not into a later change order
  • Check whether target customers are running TOPCon lines today or are still on PERC, and for how long
  • Tie feedstock contracts to the purity and lifetime evidence n-type qualification will require
  • Confirm ALMM applicability, timing and grandfathering against the final order and the relevant project category
JRST as the solution partner

How JRST supports this requirement

JRST works with manufacturers and project owners planning n-type ingot and wafer capacity: product and specification definition, resistivity and lifetime acceptance criteria, format and thickness headroom, crucible, graphite hot-zone and feedstock purity requirements, equipment scope and line balance, metrology and traceability records, supplier coordination, installation and commissioning sequencing. Final capability, warranty, performance and compliance commitments are defined against the customer's documented requirement.

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Mohammed Saif Zaveri, Co-Founder of JRST Technology
Founder perspective

Mohammed Saif Zaveri connects JRST's industrial content to execution conversations.

As Co-Founder and designated partner of JRST Technology LLP, Mohammed Saif Zaveri works across industrial growth, strategic partnerships, client conversations, equipment strategy, and project pathways for silicon, solar, semiconductor, and advanced-manufacturing opportunities.

This knowledge page is part of JRST's public industrial knowledge base, designed to help buyers move from search terms and early research toward a structured technical-commercial discussion.

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Buyer questions

Frequently asked questions

What is the difference between n-type and p-type silicon wafers?

The dopant. P-type wafers are typically boron-doped, n-type wafers phosphorus-doped. That single change removes the boron-oxygen complexes responsible for light-induced degradation and gives n-type material substantially better tolerance of metallic impurities such as interstitial iron, along with higher minority-carrier diffusion lengths at comparable impurity levels.

Has n-type actually replaced p-type in the market?

Largely, yes. N-type TOPCon overtook p-type PERC in market share during 2024, and ITRPV's 2026 edition reports n-type wafers at approximately 82% of production in 2025, projecting more than 98% within ten years. Coverage of the same roadmap reports p-type falling below 5% share by 2035.

Why is n-type harder to grow than p-type?

Mainly dopant segregation. Phosphorus has a segregation coefficient of about 0.35 against roughly 0.7 for boron, so resistivity varies more along the length of an n-type ingot and a smaller fraction of the crystal falls inside a given resistivity window. N-type cells are also qualified on bulk lifetime, which tightens oxygen, carbon and metallic contamination control across feedstock, crucible and hot zone.

How thin are n-type wafers getting?

P-type as-cut thickness has broadly stabilised near 130 µm while n-type continues toward 120 µm, and ITRPV's 2026 edition projects G12 IBC wafers reaching 110 µm within its projection period. Thinner wafers raise slicing difficulty and breakage risk, so thickness headroom should be specified upfront rather than assumed.

Is India's cell industry on n-type yet?

Partially. Reporting on the ALMM List-II position in July 2026 put enlisted cell capacity at around 30.98 GW across 15 manufacturers, with mono PERC still the largest block at roughly 52% and TOPCon at about a third. A domestic wafer producer therefore serves a mixed near-term market against a global roadmap that is firmly n-type.

Does the n-type shift change ALMM planning for wafer projects?

It changes the product specification rather than the compliance dates. MNRE has extended ALMM to ingots and wafers with effect from 1 June 2028, and wafer enlistment requires equivalent ingot capacity. Applicability, timing and grandfathering should be confirmed against the final order and the specific project category.

How can JRST help with an n-type wafer project?

JRST can help define the product and specification first — dopant route, resistivity and lifetime acceptance windows, format and thickness targets — then translate it into equipment scope, consumables and hot-zone requirements, utilities, metrology and traceability planning, supplier coordination, installation and commissioning sequencing. Warranty, performance and compliance commitments remain project-specific.

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