What project owners need to know.
Thin silicon wafers rarely break because they are thin alone. They break because silicon is brittle, and a small crack or edge flaw concentrates stress until a normal handling load is enough to fracture the wafer. Published research has found that surface and edge defects, not bulk silicon, control wafer strength; that removing the saw-damage layer raised the strength of tested multicrystalline wafers by about 50%; and that edge defects created when bricks are shaped before wafering can matter more to strength than the slicing itself. With TOPCon wafers now around 130 µm and heterojunction wafers thinner, breakage should be treated as a property the wafer maker builds in and the cell line inherits, with the test method, the flaw sources and the breakage allowance agreed in writing.
Thin is not the problem. Flaws are.
Silicon has a very high intrinsic strength and almost no tolerance for cracks. Fracture mechanics explains why: stress rises sharply at a crack tip, so once a microscopic flaw exists, only a moderate load is needed to break the wafer. Researchers at EMPA and the University of Neuchâtel put it simply: the challenge of thin-wafer manufacturing moved from slicing to handling and cleaning, and to every downstream cell step.
Thickness enters through the load path. Under the same force, a thinner wafer sees higher bending stress, so the same flaw population produces more breakage. That is why the industry has slowed thinning. TaiyangNews, reporting the ITRPV roadmap, gives around 130 µm for TOPCon and 120 µm for heterojunction in 2026, and its 2026 technology-trends coverage notes only limited scope for further thinning of TOPCon wafers. Every further micron now has to be earned in flaw control.
- Treat breakage as a flaw-population problem, not only a thickness problem
- Expect the same handling line to break more wafers as thickness falls
- Tie any thinning step to a matching improvement in flaw control
- Keep thickness headroom in the equipment specification
Where the flaws come from
A TU Delft and ECN study published in Photovoltaics International found that the fracture strength of processed wafers was mainly set by four things: the thickness of the saw-damage layer, surface roughness, cracks and defects at the edges, and, in multicrystalline material, the number of grain boundaries. Removing the damage layer by etching raised characteristic strength from about 155 MPa to 234 MPa in their tests, roughly 50%, because it shortened or blunted surface microcracks. Those were 200 µm multicrystalline laboratory specimens, so the direction of the result matters more than the numbers for today's n-type monocrystalline wafers.
The edges matter more than most specifications admit. The EMPA-led study found that edge defects created while shaping silicon bricks, before wafering, had a greater influence on measured strength than the slicing process itself. In practice, squaring, grinding and chamfering are strength steps, not just geometry steps, and edge chipping on an as-cut wafer is an early sign of breakage further down the line. The cutting side of this story, including how breakage rises through the cut, is covered in our diamond-wire slicing guide.
- Control saw-damage depth, not only surface appearance
- Treat brick squaring and edge grinding as strength-critical steps
- Inspect and trend edge chips as a leading breakage indicator
- Link crack inspection data back to the station that created the flaw
Strength changes on the cell line
A wafer's strength is not fixed at delivery. A Fraunhofer CSP and Hanwha Q CELLS study, also in Photovoltaics International, measured around 800 wafers and cells taken from 19 positions along a production line and found dramatic changes in strength between process steps as the defect structure changed. Some steps added damage and others did not. The authors described the resulting strength profile as a fingerprint of a cell line's yield and breakage behaviour, because it can reveal the step that creates damage even when the wafer actually breaks further downstream.
Metallisation and firing also move the numbers. In the TU Delft work, the rear aluminium paste type, the drying temperature and the peak firing temperature all changed cell strength, and higher firing temperatures raised strength while also increasing cell bow. Those results come from an older aluminium back-surface-field architecture, but the principle carries over: thermal and metallisation steps change the stress state, so breakage at stringing or lay-up is not automatically a wafer defect.
- Map strength or breakage by process position, not only as a line total
- Do not assume the station where a wafer breaks is where it was damaged
- Re-check handling margins after any change to firing or metallisation
- Share breakage data between wafer supplier and cell line
A strength number means nothing without its test method
Wafer strength is usually measured by bending samples to fracture and analysing the results with Weibull statistics, which give a characteristic strength and a modulus describing the spread of flaws. The test choice changes the answer. The EMPA-led study found that 4-line bending gave a stress-to-rupture about four times lower than ring-on-ring testing, because the two load the wafer differently. 4-line bending stresses the edges, while ring-on-ring loads the centre of the surface. The authors also found that the contact between wafer and supports affected the result, and they noted a lack of international standards for PV wafer strength testing.
For a buyer, the practical lesson is simple. A strength figure from one supplier cannot be compared with another's unless the method, sample geometry, fixture and number of samples are the same. Specify the method alongside the figure, and use the two tests for different questions: edge-sensitive bending for overall handling strength, and ring-on-ring when examining the sawing process.
- Name the test method, fixture and sample count with any strength figure
- Report Weibull characteristic strength and modulus, not a single average
- Use edge-sensitive tests when judging handling robustness
- Re-test after any change in squaring, slicing or cleaning recipe
Writing breakage into the supply agreement
Handling and transport add their own loads. Research cited by the TU Delft authors analysed stresses and breakage during handling and transport specifically, and every hand-off point, from the wafer sorter and packing to shipping, unpacking and loading at the cell line, is a chance to find an existing flaw. Automated inline handling reduces the number of contacts, and equipment makers now describe thinner wafers, higher yields and more automation as the direction for wafering. But automation only changes how often a flaw gets tested, not whether it exists.
For Indian projects, this becomes a commercial question as domestic wafer supply builds toward the ALMM List-III requirement for wafers from June 2028. A new wafer plant and its first cell-line customers will argue about breakage unless they agree it in advance. That agreement should cover the allowance at incoming inspection, how cracks are classified and imaged, how packing and transit damage is separated from wafer defects, and the joint investigation route when breakage rises. None of that needs cost figures. It needs a shared definition of what a broken wafer is and whose flaw caused it.
- Agree a breakage allowance at incoming inspection, with crack classification
- Specify packing, cushioning and transit handling alongside the wafer spec
- Keep crack images and lot traceability so root cause can be assigned
- Set a joint investigation route before the first commercial shipment
How JRST supports this requirement
JRST supports solar ingot, wafer and cell projects on wafer specification, acceptance and breakage terms, equipment scoping across squaring, slicing, cleaning and handling, and supplier qualification. Figures on this page are drawn from published research, industry roadmaps and trade reporting and should be validated for the specific project; several cited studies used laboratory specimens or older cell architectures, and breakage outcomes depend on materials, equipment, handling and operating conditions.
Discuss your requirement
Mohammed Saif Zaveri connects JRST's industrial content to execution conversations.
As Co-Founder and designated partner of JRST Technology LLP, Mohammed Saif Zaveri works across industrial growth, strategic partnerships, client conversations, equipment strategy, and project pathways for silicon, solar, semiconductor, and advanced-manufacturing opportunities.
This knowledge page is part of JRST's public industrial knowledge base, designed to help buyers move from search terms and early research toward a structured technical-commercial discussion.
View Mohammed Saif Zaveri's profileConnect on LinkedInFrequently asked questions
Why do thin silicon wafers break?
Because silicon is brittle and flaws concentrate stress. A small crack or edge chip lets a normal handling load reach fracture. Thinner wafers see higher bending stress under the same force, so the same flaws cause more breakage.
How thick are solar wafers today?
TaiyangNews, reporting the ITRPV roadmap, gives around 130 µm for TOPCon and about 120 µm for heterojunction in 2026, with limited scope for further thinning of TOPCon wafers.
What controls wafer strength?
Published research points to saw-damage layer thickness, surface roughness, edge cracks and defects, and in multicrystalline material the number of grain boundaries. Removing saw damage raised strength by about 50% in one TU Delft / ECN study.
Do edges matter more than the wafer surface?
Often, yes. An EMPA-led study found edge defects from brick shaping before wafering had a greater influence on measured strength than the slicing process itself.
How is wafer strength measured?
Usually by bending samples to fracture (4-line or 4-point bending, or ring-on-ring) and analysing results with Weibull statistics. Different methods give very different numbers, so the method must be stated with any figure.
Where does breakage happen on a cell line?
It can occur at any handling or thermal step, but the break is often not where the damage was created. Measuring strength by process position helps locate the step that introduces the flaw.
How can JRST help?
JRST supports wafer and cell projects on wafer specification, incoming-inspection terms, equipment scoping for squaring, slicing and handling, and supplier qualification. Outcomes remain project-specific and must be validated.
Primary sources and further reading
Last reviewed 2026-09-28. Technical scope, policy eligibility, availability, and commercial terms should be independently confirmed for each project.