JRST Technology
Cell Manufacturing

TOPCon Cell Lines: One Name, Four Different Process Flows

TOPCon is a family of cell architectures, not a single process. What the generations differ on, how the deposition route shapes the line, what the cell process demands from the wafer, and what Indian cell projects should establish before signing an equipment scope.

Direct answer

What project owners need to know.

TOPCon — tunnel oxide passivated contact — is the dominant crystalline silicon cell architecture, at around 75% of c-Si cell production in 2025 according to the ITRPV 17th edition. But the word describes a family rather than one process flow. PV-Manufacturing.org sets out four successive generations, from a homogeneous boron emitter on a converted PERC line through selective emitters, laser-assisted contact firing and patterned poly-Si. They share a tunnel oxide and a doped polysilicon layer; they differ in step count, laser content, cycle time and what they need from the incoming wafer. For an Indian project buying a cell line, the useful question is not whether the quotation says TOPCon. It is which generation the flow describes, which deposition route it assumes, and what wafer specification it was optimised against.

~75%TOPCon share of c-Si cell production in 2025 (ITRPV 17th ed.)
30.3 GWALMM List-II enlisted cell capacity at the 7th revision, 30 Apr 2026
~88 mgAverage silver per M10 TOPCon cell in 2025
01

Four generations behind one word

PV-Manufacturing.org describes a baseline TOPCon flow that runs front-side pyramid texturing, a uniform boron diffusion to form the p+ emitter, boron silicate glass removal, rear polishing, tunnel oxide growth, poly-Si deposition, phosphorus doping or annealing, cleaning, an AlOx/SiNx stack on the front with SiNx at the rear, screen-printed silver and firing, a light or current injection treatment, and I-V testing. That is TOPCon 1.0 — simple to implement on a converted PERC line, but with what the same source calls an inherent trade-off between contact resistance and Auger recombination because the emitter is homogeneous.

The later generations attack that trade-off in different ways. TOPCon 2.0 adds a selective emitter built from a light diffusion, laser doping and a healing diffusion, gaining open-circuit voltage and fill factor but requiring precise spatial alignment and adding cycle time. TOPCon 3.0 pairs a uniform light boron emitter with laser-assisted contact firing, which allows partially contacted metallisation and so limits the silicon-metal contact area and its recombination. TOPCon 4.0 patterns the poly-Si by laser ablation to cut parasitic absorption. Each step up buys performance with process complexity, and each changes the equipment list.

  • Ask which TOPCon generation a quoted flow actually implements
  • Count the laser steps — they drive alignment, cycle time and yield risk
  • Selective emitter and patterned poly-Si are not free additions to a 1.0 line
  • Match the generation to the efficiency the offtake contract is written against
02

The deposition route shapes the whole line

Two choices sit at the centre of the flow. The tunnel oxide can be grown by wet chemical, UV, thermal or plasma oxidation. The poly-Si layer can be deposited by LPCVD, PECVD, APCVD or PVD. These are not interchangeable line options that can be settled later; they determine tool count, doping strategy and the cleaning steps around them.

The doping consequence is the sharpest. Published work on large-area n-TOPCon cells notes that the LPCVD route cannot dope in situ and therefore has to be completed as a four-step method, while PECVD supports in-situ phosphorus doping and removes the separate doping step. That same study deposited at 420 °C and reported a best group at 24.85% efficiency with an open-circuit voltage of 705.7 mV and a fill factor of 84.74%, on n-type Czochralski wafers.

None of this makes one route universally correct. It makes the route a decision to take deliberately, with the wet-chemical scope, annealing capacity and edge-isolation strategy sized against it rather than inherited from a reference layout.

  • Fix the tunnel oxide and poly-Si routes before freezing the tool list
  • LPCVD without in-situ doping implies an extra doping and handling loop
  • Size wet-bench and anneal capacity against the chosen route, not a generic flow
  • Confirm which route the vendor's quoted efficiency was demonstrated on
03

What the cell line asks of the wafer

A TOPCon line is a demanding wafer customer. The study cited above used n-type Czochralski wafers at 1.0–1.2 Ω·cm resistivity in a 182 × 182 mm format at 0.14 mm thickness — a reminder that resistivity window, format and thickness are process inputs, not commercial preferences. ITRPV's 17th edition puts n-type monocrystalline silicon at roughly 82% of the c-Si wafer market in 2025 and expects TOPCon wafer thickness to fall from 130 µm in 2026 toward about 120 µm by 2036.

Thinner wafers at a tighter resistivity window raise the cost of variation. Breakage in handling, resistivity drift along the ingot, surface and bulk contamination and lifetime scatter all show up as cell-line yield rather than as a wafer complaint. For an integrated project, that argues for agreeing the wafer specification and its measurement methods with the cell process owner at design stage — including who tests what, on which sample plan, and what happens to a lot that sits at the edge of the window.

  • Treat resistivity window, format and thickness as process parameters
  • Plan handling and breakage control for wafers trending below 130 µm
  • Agree wafer acceptance tests and sample plans with the cell process owner
  • Keep wafer lots traceable to growth runs so yield loss can be traced back
04

Metallisation is where the roadmap is moving

Screen-printed silver remains the industrial standard and the most closely watched consumable on a TOPCon line. ITRPV's 17th edition reports average silver use for an M10 TOPCon cell at approximately 88 mg in 2025, roughly 10 mg per watt, and projects a decline to around 57 mg by 2036 through finer metallisation, laser-assisted contact firing and copper-based approaches.

Laboratory work is moving faster than the roadmap. Fraunhofer ISE reported in April 2026 an inline electroplating process combining ultrashort-pulse UV laser structuring with electrochemical deposition of nickel, copper and silver, cutting silver from 10–12 mg/Wp to 1.1 mg/Wp while reaching 24% on M10-sized TOPCon cells and a fill factor of 82.1 ± 0.3% across a 186-cell batch. The institute's own framing is that nickel/copper electroplating could become firmly established in the market within two to three years, which is a statement of direction, not of present availability.

For a project being specified now, the practical response is to keep the metallisation section of the line reviewable — printer generation, laser-assisted firing capability and floor space — rather than to bet the plant on either the current consumable or an emerging one.

  • Track silver per watt as a line KPI, not only paste price
  • Ask whether the line supports laser-assisted contact firing
  • Leave the metallisation bay physically and electrically extensible
  • Treat plating claims as roadmap, not as qualified production capability
05

The Indian policy frame around a cell line

ALMM List-II for solar cells came into force on 1 June 2026, requiring approved domestic cells in specified government and government-supported projects, and in net-metering and open-access projects commissioned on or after that date, with case-by-case extensions available through a dedicated portal for projects already well advanced. Enlisted capacity has risen through successive revisions — from 26 GW at the fourth revision in early 2026 to more than 30.3 GW at the seventh revision as of 30 April 2026, with the MNRE ALMM page recording a ninth revision on 21 August 2026.

The upstream half of that frame is already visible. Trade reporting of the March 2026 amendment describes wafers entering the ALMM framework from June 2028, with an initial publication covering 13 GW across six manufacturers. A cell project commissioned in the next two years will therefore be sourcing wafers into a regime that is itself being enlisted. Lining up the two — cell enlistment now, qualified wafer supply for 2028 — is a planning question worth taking early, and the current requirement should always be confirmed directly with MNRE rather than from summaries.

  • Check the live MNRE revision before relying on any capacity or scope figure
  • Plan cell enlistment and wafer supply qualification as one timeline
  • Document commissioning evidence early if an extension may be needed
  • Confirm current ALMM requirements directly with the relevant authority
JRST as the solution partner

How JRST supports this requirement

JRST supports ingot, wafer and cell projects where equipment scope meets process reality: reading a quoted TOPCon flow against the generation it actually implements, aligning wafer specification and acceptance testing with the cell process that will consume it, and sequencing scope so that upstream supply and downstream enlistment land together. Figures on this page are drawn from public technical sources, industry roadmaps and policy reporting and should be validated for the specific project; process performance depends on material, equipment and operating conditions, and compliance requirements must be confirmed with the relevant authorities.

Discuss your requirement
Mohammed Saif Zaveri, Co-Founder of JRST Technology
Founder perspective

Mohammed Saif Zaveri connects JRST's industrial content to execution conversations.

As Co-Founder and designated partner of JRST Technology LLP, Mohammed Saif Zaveri works across industrial growth, strategic partnerships, client conversations, equipment strategy, and project pathways for silicon, solar, semiconductor, and advanced-manufacturing opportunities.

This knowledge page is part of JRST's public industrial knowledge base, designed to help buyers move from search terms and early research toward a structured technical-commercial discussion.

View Mohammed Saif Zaveri's profileConnect on LinkedIn
Buyer questions

Frequently asked questions

What does TOPCon mean in a cell line quotation?

It names an architecture — a tunnel oxide with a doped polysilicon passivating contact — not a specific process flow. PV-Manufacturing.org describes four generations that differ in emitter design, laser content and poly-Si patterning, so the generation and step list matter more than the label.

What is the difference between LPCVD and PECVD for the poly-Si layer?

PECVD supports in-situ phosphorus doping, while the LPCVD route cannot dope in situ and is completed as a four-step method with a separate doping stage. That changes tool count, handling and the cleaning steps around deposition.

How dominant is TOPCon today?

The ITRPV 17th edition puts TOPCon at around 75% of crystalline silicon cell production in 2025 and expects it to remain the leading technology through 2036, with back-contact and tandem architectures growing alongside it.

What wafer does a TOPCon line need?

N-type monocrystalline silicon, which ITRPV places at roughly 82% of the c-Si wafer market in 2025. Published large-area n-TOPCon work used 1.0–1.2 Ω·cm n-type Czochralski wafers at 182 × 182 mm and 0.14 mm thickness; the exact window should be agreed with the cell process owner.

How much silver does a TOPCon cell use?

ITRPV reports approximately 88 mg per M10 cell in 2025, about 10 mg per watt, falling to around 57 mg by 2036 on the current roadmap. Fraunhofer ISE has demonstrated a plating route at 1.1 mg/Wp in research, which it expects could establish itself in the market within two to three years.

When does ALMM List-II apply to solar cells in India?

It came into force on 1 June 2026 for specified government and government-supported projects and for net-metering and open-access projects commissioned on or after that date, with case-by-case extensions available for advanced projects. Enlisted capacity and scope change with each revision, so confirm the current position with MNRE.

How can JRST help with a cell line project?

JRST can help interrogate a quoted process flow against the generation it actually implements, align wafer specification and acceptance testing with the cell process, and frame equipment scope and sequencing for Indian projects. Performance and compliance outcomes remain project-specific and must be validated.

Begin with the requirement, not a catalogue.

Turn the research into a project route.

Book a consultation