Wafer Texturing & Cleaning: From As-Cut Wafer to Cell-Ready Surface

Why an as-cut wafer is not ready for a cell

A wafer that comes off a diamond-wire saw is flat, shiny and damaged. The sawing leaves a thin layer of cracked, stressed silicon at the surface, along with residues from the slicing process. A polished, flat silicon surface also reflects a large share of incoming light. Before any junction or passivation layer is added, the cell maker therefore runs the wafer through a wet-chemical sequence: remove the damage, texture the surface, and clean it.

These steps usually run at the start of the cell line rather than in the wafer plant, but they are where the wafer's own quality first shows. Surface residues, contamination and saw marks that leave the wafer plant carry straight into texturing.

Saw damage etch: removing the cracked layer

Saw damage etch (SDE) strips the damaged surface layer left by wire sawing. It uses a much stronger alkaline bath than texturing, because the goal is to remove silicon quickly and evenly rather than to shape it, according to the PV-Manufacturing.org process guide.

The trend is to do less of it. Thinner wafers and cleaner diamond-wire cuts leave less damage, and every micrometre etched away is silicon that was paid for. TaiyangNews reported in 2023 that for TOPCon lines, SDE is either eliminated or very low, and that RENA's best results came with very little saw damage etch and strongly reduced KOH consumption. Research groups, including a 2023 Fraunhofer ISE study on heterojunction cells, have reported short SDE times or no separate SDE step giving cell results as good as longer etches.

Alkaline texturing: how the pyramids form

Texturing exploits silicon's crystal structure. Alkaline etchants such as potassium hydroxide (KOH) etch the (100) planes of silicon much faster than the (111) planes. On a (100)-oriented monocrystalline wafer, this leaves a surface covered in small upright pyramids whose sides are (111) planes. PVEducation describes this random pyramid texture as the standard industry approach for single-crystal wafers.

The pyramids help in three ways: light reflected off one face often strikes another and enters the silicon; light that enters is refracted at an angle and travels a longer path; and long-wavelength light reflected from the rear is more likely to be trapped inside. Pyramid size has been shrinking. PV-Manufacturing.org describes an optimal pyramid base edge of a few micrometres with near-complete surface coverage, while TaiyangNews reported in 2023 that RENA found an optimal TOPCon pyramid size close to 1 µm.

• The bath is far more dilute and slower than the SDE bath; a slow etch makes it more selective between crystal planes
• Isopropanol (IPA) has long been used as a wetting agent so hydrogen bubbles do not stick to the surface; equipment makers now offer additive-based and IPA-free processes
• Industry reflectivity goals reported in 2023 were below 10% at 600 nm for PERC and below 9% for TOPCon, before any anti-reflection coating
• The process is sensitive to the starting surface, including residual silicates from the damage etch and contamination from slicing

Cleaning: RCA, HF and ozone

After texturing, the surface must be free of organic residues, metal ions and uncontrolled oxide before the next high-temperature or deposition step. The reference point is the RCA clean, published by Werner Kern and D. A. Puotinen in RCA Review in June 1970: an alkaline ammonia-and-peroxide step (SC-1) that lifts particles and organics, and an acidic hydrochloric-acid-and-peroxide step (SC-2) that removes metal contamination, typically combined with a dilute hydrofluoric acid (HF) dip to strip the oxide.

Solar lines use leaner versions of this logic. Equipment sequences reported by TaiyangNews include a pre-clean, alkaline texturing, rinses, a metal and ozone clean and drying, with high-throughput wet benches handling in the order of 10,000 or more wafers per hour.

What TOPCon and heterojunction change

Higher-efficiency cells are less forgiving. In a heterojunction (HJT) cell, thin amorphous silicon layers passivate the textured surface directly, so the shape and cleanliness of the pyramids matter more. A Fraunhofer ISE study presented at SiliconPV 2023 found that ozone-based rounding of the pyramid tips increased reflection and lowered current, but improved passivation enough that about two minutes of rounding gave the best cell efficiency; the benefit levelled out at module level.

TOPCon lines have moved to smaller, denser pyramids and minimal saw damage etch, with additives designed for their structure. Both trends point the same way: the closer the as-cut wafer is to clean, undamaged and uniform, the less the cell line has to correct.

What this means for wafer makers in India

As India builds ingot and wafer capacity under ALMM List-III, which is proposed to apply to ingots and wafers from 1 June 2028, cell makers will judge domestic wafers partly by how they texture. Uniform crystal orientation from the ingot, controlled saw damage, low surface contamination after slicing, and consistent wafer cleaning and packing all show up as texture uniformity and reflectivity at the cell plant.

Wet benches also bring practical obligations: handling of strong alkalis and acids, high water use, and effluent treatment that needs to be planned with the relevant state pollution control board. This guide is general awareness, not a process recipe. Chemistries, settings and acceptance limits depend on the cell architecture and equipment, and should be validated with the cell maker and the equipment supplier.