What project owners need to know.
A cleanroom classification describes airborne particle concentration and nothing else. ISO 14644-1 sorts clean environments into nine classes using particle counts between 0.1 µm and 5.0 µm, but a silicon ingot and wafer line loses yield to contamination that no particle counter detects: molecular acids, bases and dopants at parts-per-billion levels, and trace metals that arrive on the wafer surface from feedstock, crucibles, hot-zone parts, process chemicals, tooling and carriers. SEMI maintains separate standards for each of these because they are separate problems. A credible contamination plan for an Indian wafer project therefore names the room class, the molecular specification, the surface-metal element package and the measurement method that will be used to prove all three — before equipment is ordered, not after a qualification lot fails.
The class number is not the contamination plan
ISO 14644-1 classifies air cleanliness by the concentration of airborne particles, using nine classes and threshold sizes from 0.1 µm to 5.0 µm. The published limits span a very wide range: ISO Class 1 permits 10 particles per cubic metre at 0.1 µm and above, while ISO Class 9 permits 35,200,000 particles per cubic metre at 0.5 µm and above, with 0.5 µm remaining the core index used to evaluate an environment. The classes are related by a fixed exponent, so a count at one size implies the limit at another.
That is a useful specification for the air, and an incomplete one for a wafer. Particle counting says nothing about molecular contaminants, nothing about metals already on the incoming wafer surface, nothing about what a graphite or quartz part sheds into a hot zone, and nothing about what a carrier outgasses onto a stored wafer. Projects that specify only a class number tend to discover the gap during qualification, when the electrical result disagrees with a clean room log.
- State the class, the occupancy state and the monitoring plan, not the class alone
- Treat particle, molecular and surface-metal control as three separate specifications
- Match the classification to the step: growth, wafering, cleaning and inspection are not one environment
- Write the acceptance evidence for each control into the project documentation early
Where contamination actually enters a silicon line
In ingot and wafer production the dominant contamination routes are material routes, not doorways. Silicon feedstock, the quartz crucible, graphite and carbon-fibre hot-zone components, process gases, cleaning chemistry, ultrapure water, cutting and handling tooling, consumable wear parts and wafer carriers each contribute their own signature. Personnel and air movement matter, but they are rarely the whole story in a crystal-growth hall.
This is why hot-zone and consumable purity should be specified as a critical-element package rather than a single headline number. Total ash or a generic purity grade does not distinguish between elements that are electrically benign and elements that are not, and it does not describe batch-to-batch variation. The relevant SEMI test methods point the same way: SEMI E180 defines quantitative measurement of surface trace metals on critical chamber components such as showerheads and pedestals against a named list of thirteen metals including aluminium, sodium, potassium, calcium, lithium, iron, copper, nickel, chromium, cobalt, titanium, magnesium and zinc. Components are treated as a measurable contamination source in their own right.
- Map every material that touches, heats or encloses the silicon and assign it a purity specification
- Specify consumables by element package and batch evidence, not by grade name alone
- Include wear parts, tooling and carriers in the contamination map
- Ask suppliers for the measurement method behind any purity claim
Molecular contamination is a separate specification
SEMI F21 exists to classify microelectronics clean environments by their molecular, non-particulate contaminant levels, and is written to be used both for specifying clean environments including process-tool environments and for evaluating the performance of contamination-control and measurement equipment. Its contaminant groups are typically described as acids, bases, condensables and dopants, and the concentrations of interest sit at parts-per-billion and parts-per-trillion levels rather than anything a particle counter reports.
The failure modes are correspondingly different from particle defects: corrosion of metal features, haze and condensable residue on optical and wafer surfaces, unintended doping, and degradation that appears well after the process step that caused it. For a wafer plant, the practical consequence is that filtration, make-up air treatment, chemical storage and exhaust routing need to be argued against a molecular specification, and that the specification should name what will be sampled and how often.
- Specify molecular limits separately from the particle class
- Identify the acid, base, condensable and dopant sources on site, including storage and exhaust
- Define the sampling method, location and frequency in the monitoring plan
- Distinguish room-level control from point-of-use control at sensitive tools
Measure the surface, not just the room
The wafer is the only surface whose cleanliness the customer actually buys. SEMI M85 describes measuring trace metal contamination on semiconductor-grade silicon wafer surfaces by inductively coupled plasma mass spectrometry, covering mirror-polished, annealed, epitaxial, diffusion and bonding wafers with non-patterned surfaces as well as the backside of patterned wafers, and naming an element set that includes sodium, magnesium, aluminium, potassium, calcium, chromium, manganese, iron, cobalt, nickel, copper and zinc. It uses scanning solutions of hydrofluoric acid with hydrogen peroxide or nitric acid, validated against a recovery range of 75 to 125 percent. A purity claim without a method and a recovery window is not a measurement.
Cleaning chemistry is the other half of the surface story, and its effect is large. The classical RCA sequence remains the reference: SC-1 as ammonium hydroxide, hydrogen peroxide and water at a nominal 1:1:5 for organics and certain metals, SC-2 as hydrochloric acid, hydrogen peroxide and water at a nominal 1:1:6 for heavy metal ions. A 2023 review of surface cleaning and passivation for silicon heterojunction cells reports effective carrier lifetimes spanning roughly 8 µs on poorly prepared surfaces to 5.8 ms with an optimised ozone-based clean on the samples studied. Those are specific experimental results rather than a universal benchmark, but the direction is unambiguous: on lifetime-sensitive products, surface preparation is a process parameter, not a housekeeping step.
- Define the surface-metal element list and limits in the product specification
- Require the analytical method, detection capability and recovery validation with every result
- Treat cleaning chemistry, rinse quality and drying as controlled process steps
- Use lifetime or photoluminescence measurement as the electrical check on contamination control
Why this is becoming an India question
India's compliance surface is moving upstream. MNRE's public ALMM page records the first solar PV module list on 10 March 2021 and the first cell list on 31 July 2025, both updated through August 2026. ALMM List-III extends the framework to wafers from 1 June 2028; trade reporting of the March 2026 rules states that the initial wafer list is to be issued only once at least three independent wafer manufacturing facilities are operational in India with a combined minimum annual capacity of 15 GW, that a manufacturer seeking List-III enlistment must hold equivalent ingot capacity, and that a seven-day cut-off governs which bids fall under the requirement after the list is first published. Domestic wafer lines will therefore have to demonstrate consistent, documented quality rather than simply produce output.
Interfaces deserve the same scrutiny, because standards often stop short of where a project assumes they end. SEMI E47.1, the mechanical specification for FOUPs used to transport and store 300 mm wafers, states plainly that only the physical interfaces are specified and that no materials requirements or microcontamination limits are given, even though the enclosure can serve as a sealed minienvironment. A carrier that is dimensionally standard is not automatically a clean carrier. Cleanliness for handling and storage has to be contracted and verified separately, on the materials and on the measured result.
- Build the contamination evidence file alongside the production plan, not after it
- Check current MNRE pages before writing any wafer-list assumption into a bid or supply contract
- Contract carrier, tooling and packaging cleanliness explicitly; dimensional standards do not cover it
- Keep calibration, sampling and analytical records traceable to specific production lots
How JRST supports this requirement
JRST supports the technical-commercial interface on contamination control: mapping where contamination enters a specific ingot and wafer route, specifying consumable and hot-zone purity as a critical-element package with batch evidence, separating the particle, molecular and surface-metal specifications so each has a named measurement method, and carrying those requirements into equipment RFQs, supplier qualification and acceptance planning. Figures on this page are drawn from published standards scopes and public research and should be validated for the specific project; cleanroom classification, facility engineering, safety review and regulatory compliance must be confirmed by the responsible engineers, suppliers and authorities for the site in question.
Discuss your requirement
Mohammed Saif Zaveri connects JRST's industrial content to execution conversations.
As Co-Founder and designated partner of JRST Technology LLP, Mohammed Saif Zaveri works across industrial growth, strategic partnerships, client conversations, equipment strategy, and project pathways for silicon, solar, semiconductor, and advanced-manufacturing opportunities.
This knowledge page is part of JRST's public industrial knowledge base, designed to help buyers move from search terms and early research toward a structured technical-commercial discussion.
View Mohammed Saif Zaveri's profileConnect on LinkedInFrequently asked questions
What cleanroom class does a silicon wafer plant need?
There is no single correct answer, because the requirement varies by step and by product. ISO 14644-1 provides the classification framework across nine classes and particle sizes from 0.1 µm to 5.0 µm, but the class must be selected against the specific process step, the product's sensitivity and the customer's acceptance requirement. Crystal growth, wafering, cleaning and inspection areas are usually treated differently.
Is a cleanroom class enough to control contamination?
No. A class describes airborne particle concentration only. Molecular contamination, surface trace metals, consumable and hot-zone purity, chemical and water quality, and carrier cleanliness are all specified separately, by different standards and different measurement methods.
What is airborne molecular contamination?
It is gaseous, non-particulate contamination present at parts-per-billion and parts-per-trillion levels. SEMI F21 classifies clean environments by molecular contaminant level; the groups are typically described as acids, bases, condensables and dopants. The associated failure modes include corrosion, condensable residue and unintended doping.
How is trace metal contamination on a wafer measured?
SEMI M85 describes measurement of trace metal contamination on semiconductor-grade silicon wafer surfaces by inductively coupled plasma mass spectrometry, with a defined element set and scanning solutions of hydrofluoric acid with hydrogen peroxide or nitric acid, validated against a recovery range of 75 to 125 percent. Any supplier purity claim should be accompanied by its method and validation.
Do wafer carriers guarantee cleanliness?
Not on their own. SEMI E47.1 states that only the physical interfaces of 300 mm FOUPs are specified and that no materials requirements or microcontamination limits are given. Carrier materials, cleaning and outgassing behaviour have to be specified and verified separately.
How does contamination control connect to ALMM List-III?
ALMM List-III extends the framework to wafers from 1 June 2028, with reported conditions on the number of operational facilities, combined capacity and equivalent ingot capacity before the initial list is issued. Domestic wafer lines should expect to demonstrate documented, repeatable quality, which makes contamination evidence part of the production plan rather than an afterthought.
How can JRST help with contamination control planning?
JRST can help define the contamination map for a specific line, specify consumable and hot-zone purity as an element package, structure the particle, molecular and surface-metal specifications with their measurement methods, and carry that evidence requirement into equipment RFQs, supplier qualification and acceptance planning. Final facility engineering, regulatory compliance and process performance remain project-specific.
Primary sources and further reading
Last reviewed 2026-09-11. Technical scope, policy eligibility, availability, and commercial terms should be independently confirmed for each project.