What project owners need to know.
A back-contact (BC) solar cell places both its electron and hole contacts on the rear of the wafer, leaving the front surface free of metal grid lines. PV-Manufacturing.org notes that the highest wafer-based silicon cell efficiencies reported to date have come from this interdigitated back-contact architecture, and companies reported certified BC cell results above 28% in the first half of 2026. The ITRPV 17th edition expects TOPCon-based BC (TBC) to grow from around 5% of production in 2025 to around 23% in 2036. For India, where cell capacity is being built largely on TOPCon, the practical point is upstream: because carriers generated at the front must travel the full thickness of the wafer to reach the rear contacts, BC depends on high minority carrier lifetime material. A wafer plant specified today should know which cell architecture it may be supplying in 2030.
One idea, several architectures
The defining feature of a back-contact cell is geometry rather than chemistry. PV-Manufacturing.org describes the interdigitated back-contact (IBC) cell as having alternating contacts for electrons and holes on the rear side, formed by masked diffusion, masked ion implantation or laser doping. Removing the front grid removes its shading, which is the main source of the architecture's higher short-circuit current, and moving the metal to the rear allows wider fingers that can reduce series resistance.
What sits under the rear contacts varies, and that is where the family divides. Diffused homojunction IBC is the oldest form. TBC carries the tunnel oxide and doped polysilicon contacts familiar from TOPCon onto the rear. Heterojunction-based BC uses amorphous silicon layers instead, and hybrid designs (reported as HBC, HIBC or THBC depending on the developer) combine passivating-contact types on the same rear surface. A quotation that simply says "BC" leaves most of the line undefined.
- Ask which passivating-contact type sits under each rear polarity
- Treat TBC, heterojunction BC and hybrid BC as different lines, not options
- Confirm how the rear pattern is formed — masking, implantation or laser
- Check whether a quoted efficiency was measured on total or designated area
What the roadmap actually says
The ITRPV 17th edition, as reported by TaiyangNews in September 2026, expects TOPCon to remain the leading cell technology through 2036 while BC expands alongside it. Its forecast is that TBC grows from approximately 5% in 2025 to around 23% in 2036, and heterojunction-based BC from around 0.1% to approximately 5%. At module level, it puts mass-production efficiency at 23.9% for TOPCon, 23.9% for HJT and 24.3% for BC in 2026, rising to 25.2%, 25.3% and 25.6% in 2036 — a lead for BC, but not a large one.
The cell-level race is moving faster than the module roadmap. pv magazine reported in April and May 2026 a succession of developer claims for back-contact cells certified at 28.0%, 28.13% and 28.2%, each described by the developer as a record. Those are champion results, and the gap between a certified champion cell and a stable production average is exactly what a line buyer has to price in. Roadmap shares, not record announcements, are the better planning input.
- Plan against roadmap production shares, not champion-cell headlines
- Note that BC's module-efficiency lead over TOPCon is under one point
- Expect TOPCon and TBC to coexist rather than one replacing the other
- Re-check forecasts against each new ITRPV edition
Why BC is harder to build
Putting both polarities on one surface makes the rear side a patterning problem. PV-Manufacturing.org identifies rear-surface passivation as a key challenge, because dual dopant polarities on the same face complicate carrier selectivity. Published record work reflects the added steps: a 2024 heterojunction back-contact study reached 27.09% certified efficiency with a flow of multi-step wet cleaning, CVD, laser ablation, PVD and metallisation, including three separate laser patterning stages, and had to engineer edge passivation to hold wafer edge recombination loss below 0.1 mA·cm⁻².
The industrial consequences were visible in India early. pv magazine India reported in October 2024 that most Indian manufacturers intended to stay with TOPCon for the near term, citing heavy capital expenditure for retooling, non-standardised processes with many different routes, lower yields, and higher electrical rejects and breakages. It also reported bifaciality of around 70% for BC against about 80% for TOPCon at the time. Newer work has narrowed that gap — a 2025 TBC study reports a bifaciality factor above 80% — and equipment suppliers now describe upgrade routes from TOPCon to TBC, but the upgrade is a process project, not a tool swap.
- Count the laser patterning steps and the alignment each one demands
- Ask for yield and electrical-reject data at production scale, not pilot
- Check bifaciality if the offtake depends on bifacial gain
- Treat a TOPCon-to-TBC upgrade as a requalification, not an add-on
BC asks for a different wafer
The architecture's wafer requirement follows directly from its geometry. Light is absorbed near the front, but the contacts are at the back. PV-Manufacturing.org states that BC therefore needs high minority carrier lifetime wafer material so that photogenerated carriers can diffuse through the full thickness to the rear contacts. On a front-contact cell, some lifetime shortfall is tolerated; on a BC cell, it shows up directly as lost current.
The published record cells illustrate how different the specification can look. The 350 cm² TBC cell reported in Nature Communications in 2025 used phosphorus-doped n-type Czochralski wafers at 6–12 Ω·cm, 170 µm thick for the certified cell and 130 µm in mass production. For comparison, published large-area TOPCon work cited in our TOPCon guide used 1.0–1.2 Ω·cm, and the 2024 heterojunction BC study used 1.2–1.5 Ω·cm. The point is not that one window is correct — each developer optimises its own — but that the resistivity window, lifetime floor and thickness are set by the cell architecture, and a wafer line tuned only for one of them may need to re-tune for another.
For an ingot and wafer plant, that turns cell technology into a growth-side question: resistivity control along the ingot, oxygen and thermal history that affect lifetime, and the measurement capability to certify lifetime lot by lot.
- Agree resistivity window and lifetime floor with the target cell architecture
- Make minority carrier lifetime a measured acceptance parameter, not a nominal
- Plan resistivity control along the ingot for a possibly wider or higher window
- Keep lots traceable to growth runs so lifetime scatter can be diagnosed
What this means for Indian projects
India's cell build-out is running on TOPCon, and ALMM List-II for solar cells has been in force since 1 June 2026. Wafers enter the ALMM framework from June 2028. A wafer plant commissioning around that date will be supplying cell lines that, on ITRPV's forecast, are increasingly being upgraded toward TBC over the following decade.
That argues for specifying the wafer plant against a range of cell architectures rather than a single customer's current recipe: crystal growth able to hold tighter or different resistivity windows, lifetime metrology built into acceptance, and a thickness roadmap that assumes continued thinning. None of that requires betting on BC. It requires not locking a twenty-year wafer asset to a cell process that the roadmap already expects to share the market. Current ALMM scope and timelines should always be confirmed directly with MNRE.
- Specify wafer capability for TOPCon today and TBC tomorrow
- Build lifetime and resistivity metrology into the plant from day one
- Align wafer qualification with the 2028 ALMM List-III timeline
- Confirm current ALMM requirements directly with MNRE
How JRST supports this requirement
JRST supports ingot and wafer projects in specifying capability against where the cell market is heading, not only where it is today: resistivity control, lifetime metrology and acceptance testing aligned with TOPCon and back-contact cell requirements. Figures on this page are drawn from public technical sources, industry roadmaps and trade reporting and should be validated for the specific project; cell and wafer performance depends on material, equipment and operating conditions, and compliance requirements must be confirmed with the relevant authorities.
Discuss your requirement
Mohammed Saif Zaveri connects JRST's industrial content to execution conversations.
As Co-Founder and designated partner of JRST Technology LLP, Mohammed Saif Zaveri works across industrial growth, strategic partnerships, client conversations, equipment strategy, and project pathways for silicon, solar, semiconductor, and advanced-manufacturing opportunities.
This knowledge page is part of JRST's public industrial knowledge base, designed to help buyers move from search terms and early research toward a structured technical-commercial discussion.
View Mohammed Saif Zaveri's profileConnect on LinkedInFrequently asked questions
What is a back-contact solar cell?
A crystalline silicon cell with both its electron and hole contacts on the rear surface, so the front carries no metal grid. Removing front shading is the main reason the architecture reaches the highest reported wafer-based silicon efficiencies.
What is the difference between IBC, TBC and HBC?
IBC (interdigitated back contact) describes the rear contact layout. TBC places TOPCon-style tunnel oxide and doped polysilicon contacts on the rear; heterojunction BC uses amorphous silicon layers; hybrid designs (HBC and similar names) combine contact types on the same rear surface.
Will back-contact replace TOPCon?
Not on current forecasts. The ITRPV 17th edition expects TOPCon to stay the leading technology through 2036, with TOPCon-based BC growing from around 5% of production in 2025 to around 23% in 2036.
How efficient are BC cells?
Developers reported certified BC cells between 28.0% and 28.2% in April and May 2026. At module level, ITRPV forecasts BC mass-production efficiency of 24.3% in 2026, rising to 25.6% by 2036.
Why do BC cells need better wafers?
Most light is absorbed near the front, but the contacts are at the back, so carriers must diffuse through the whole wafer. That makes high minority carrier lifetime a hard requirement rather than a preference.
Is anyone manufacturing BC cells in India?
Public reporting has described most Indian manufacturers as staying with TOPCon in the near term because of retooling cost, process complexity and yield risk, with BC plans limited to a small number of groups. Check current announcements before relying on this.
How can JRST help?
JRST can help ingot and wafer projects frame growth, metrology and acceptance capability against the cell architectures their wafers may supply, including TOPCon and TBC. Outcomes remain project-specific and must be validated.
Primary sources and further reading
Last reviewed 2026-09-27. Technical scope, policy eligibility, availability, and commercial terms should be independently confirmed for each project.
