What project owners need to know.
Light-induced degradation is the loss of carrier lifetime, and therefore cell efficiency, that appears once silicon is exposed to light, heat or current. Several distinct mechanisms sit under that label. Boron-oxygen LID forms when interstitial oxygen from the Czochralski process pairs with boron and, per PV-Manufacturing.org, can cost up to 10% relative efficiency within about 48 hours of light at room temperature. Light and elevated temperature induced degradation (LeTID) is slower, is linked to hydrogen and cell firing, and is more pronounced at higher temperature. Copper-related LID traces back to metal contamination. Several of these causes start in the ingot and wafer: oxygen content, dopant choice and contamination. For Indian wafer suppliers preparing for ALMM List-III, degradation behaviour belongs in the specification and the qualification plan, not only in the module warranty.
One label, several mechanisms
Light-induced degradation is often discussed as a single number on a module datasheet. In the silicon it is several different defect reactions with different causes, timescales and fixes. The three that matter most to wafer buyers are boron-oxygen LID, light and elevated temperature induced degradation (LeTID), and copper-related LID. Treating them as one problem leads to the wrong fix: a dopant change that removes one mechanism does nothing for another.
The practical distinction is where each one starts. Boron-oxygen LID and copper LID are set largely by what is inside the wafer, which is decided during crystal growth and handling. LeTID is strongly shaped by the cell process, particularly hydrogen-rich passivation and firing, but it has also been observed across multicrystalline, Czochralski, float-zone and n-type material, so the wafer is not a bystander.
- Boron-oxygen LID: dopant and oxygen chemistry of the wafer
- LeTID: hydrogen, firing profile and operating temperature, across many wafer types
- Copper LID: interstitial copper contamination in the bulk
- Name the mechanism before choosing the mitigation
Boron-oxygen LID starts in the crucible
PV-Manufacturing.org describes the boron-oxygen defect as forming when interstitial oxygen, unintentionally introduced during the Czochralski process, reacts with substitutional boron. The same source reports that the recombination strength scales with the square of the oxygen concentration but only linearly with boron, that the defect can form at illumination below 0.02 suns, and that it can cause severe degradation within 48 hours at room temperature, with losses of up to 10% relative (roughly 1–2% absolute) on Cz cells.
The oxygen-squared relationship is why crystal growth matters. Oxygen in Cz silicon comes largely from the quartz crucible and is moved by melt flow and argon gas flow, so hot-zone design, crucible quality and process settings all influence how exposed a boron-doped wafer will be. Two industrial routes address it. Gallium doping removes the boron and with it the defect, but gallium's low segregation coefficient, cited as 0.008, produces a stronger resistivity gradient along the ingot and can reduce usable yield. Hydrogenation treatments that combine illumination with elevated temperature can permanently deactivate the defect at cell level. Phosphorus-doped n-type wafers contain no boron and so avoid this mechanism entirely.
- Specify and measure interstitial oxygen, not only resistivity
- If boron-doped, agree whether the cell maker will apply a deactivation step
- If gallium-doped, plan for the resistivity profile along the ingot in binning
- Treat crucible and hot-zone condition as degradation-risk variables
LeTID: slower, hotter and tied to hydrogen
LeTID shows up over longer exposure to light and heat and, according to PV-Manufacturing.org, is more pronounced at higher temperatures and can take years to decades to recover naturally. It was first studied in multicrystalline PERC cells, where it was markedly stronger than in older aluminium back-surface-field designs, and has since been reported in Czochralski, float-zone and n-type silicon. Research increasingly points to hydrogen, with hydrogen-rich silicon nitride layers fired above about 800 °C associated with stronger degradation.
Published mitigation routes are mostly process-side: adjusting peak firing temperature and cooling rates, applying accelerated degradation and regeneration steps, dark annealing, and changes to wafer thickness and properties. For testing, IEC TS 63342:2022 defines a current-injection test that detects whether c-Si modules are sensitive to LeTID. Its own scope is careful: it excludes room-temperature boron-oxygen and iron-boron effects and does not predict the exact degradation a module will see in the field.
- Ask cell customers which LeTID test and pass criterion they apply
- Do not read an IEC TS 63342 result as a field-loss prediction
- Share wafer thickness and material changes with cell customers before shipment
- Keep degradation test lots traceable to ingot and growth run
Copper LID and the case for contamination control
Copper-related LID is a reminder that degradation can be a contamination problem. PV-Manufacturing.org attributes it to interstitial copper in the bulk before illumination, notes it has been observed in p-type Cz silicon as well as float-zone, n-type and gallium-doped material, and reports that it proceeds faster at higher temperature, higher light intensity and higher copper concentration. Because it is independent of the boron-oxygen reaction, switching dopant does not solve it.
The wafer-side answer is the same discipline that protects lifetime generally: control of metals in feedstock, hot-zone parts, wire, slurry or coolant, cleaning chemistry and handling. Contactless lifetime measurement on ingots, bricks and wafers, of the kind described in SEMI PV13, gives a baseline; comparing lifetime before and after a controlled light-soak on sample wafers turns that baseline into early warning.
- Include copper and other fast-diffusing metals in incoming material checks
- Compare lifetime before and after controlled light-soak on sample lots
- Audit wire, cleaning and handling steps as possible copper sources
- Record degradation results against supplier lots for root-cause work
Why this matters for Indian wafer projects
ALMM List-III brings wafers into India's approved-list framework from 1 June 2028, and trade reporting of the March 2026 rules states that wafer enlistment requires equivalent ingot capacity. Integrated ingot-to-wafer suppliers will increasingly sell into domestic cell lines that carry long module warranties, often in hot climates where temperature-accelerated mechanisms such as LeTID are a live concern. A wafer that passes initial efficiency tests but degrades faster in the field becomes the cell maker's warranty problem and, eventually, the wafer supplier's commercial problem.
The implication is to design degradation behaviour in from the start: agree the dopant route with target customers, specify oxygen and contamination limits alongside resistivity and lifetime, define light-soak or current-injection checks for qualification lots, and keep the data link from each lot back to its growth run.
- Agree dopant strategy (boron, gallium or phosphorus) with target cell customers early
- Write oxygen, carbon and metal limits into the wafer specification
- Build degradation testing into customer qualification, not after complaints
- Confirm current MNRE requirements directly before relying on any compliance assumption
How JRST supports this requirement
JRST supports ingot and wafer projects where material decisions meet long-term cell performance: framing dopant and oxygen strategy at the growth stage, turning customer degradation requirements into wafer specifications and qualification plans, and reviewing contamination-control points from hot zone to cleaning. Figures on this page are drawn from public technical sources and standards scopes and should be validated for the specific project; degradation behaviour depends on material, cell process and operating conditions and must be confirmed through testing with suppliers, customers and the relevant authorities.
Discuss your requirement
Mohammed Saif Zaveri connects JRST's industrial content to execution conversations.
As Co-Founder and designated partner of JRST Technology LLP, Mohammed Saif Zaveri works across industrial growth, strategic partnerships, client conversations, equipment strategy, and project pathways for silicon, solar, semiconductor, and advanced-manufacturing opportunities.
This knowledge page is part of JRST's public industrial knowledge base, designed to help buyers move from search terms and early research toward a structured technical-commercial discussion.
View Mohammed Saif Zaveri's profileConnect on LinkedInFrequently asked questions
What is light-induced degradation in solar wafers?
A loss of carrier lifetime and cell efficiency after exposure to light, heat or current. It covers several mechanisms, mainly boron-oxygen LID, LeTID and copper-related LID, each with different causes and fixes.
How much efficiency can boron-oxygen LID cost?
PV-Manufacturing.org reports losses of up to 10% relative, about 1–2% absolute, on Czochralski-grown cells, developing within about 48 hours of illumination at room temperature. Actual impact depends on oxygen and boron levels and on any deactivation treatment.
Does gallium doping solve LID?
It eliminates the boron-oxygen defect, because there is no boron. It does not address LeTID or copper-related LID, and gallium's low segregation coefficient creates a stronger resistivity gradient along the ingot, which can affect yield.
Are n-type wafers immune to degradation?
Phosphorus-doped n-type wafers avoid boron-oxygen LID. They are not automatically immune to everything: LeTID and copper-related degradation have both been reported in n-type silicon.
What is LeTID and what causes it?
Light and elevated temperature induced degradation is a slower mechanism that is more pronounced at higher temperature. Research increasingly links it to hydrogen from hydrogen-rich passivation layers, with high-temperature firing affecting how strongly it appears; the mechanism is still being studied.
Is there a standard test for LeTID?
IEC TS 63342:2022 defines a current-injection test to detect LeTID sensitivity in c-Si modules. It excludes room-temperature boron-oxygen and iron-boron effects and does not provide an exact prediction of field degradation.
How can JRST help with wafer degradation risk?
JRST can help frame dopant and oxygen strategy at the crystal-growth stage, translate customer degradation requirements into wafer specifications and qualification tests, and review contamination-control points across growth, slicing and cleaning. Performance outcomes remain project-specific.
Primary sources and further reading
Last reviewed 2026-09-17. Technical scope, policy eligibility, availability, and commercial terms should be independently confirmed for each project.