What project owners need to know.
Silicon carbide substrates are not made the way silicon substrates are. There is no practical melt to pull a boule from at ordinary pressure, so bulk SiC is grown by physical vapour transport: source powder is sublimed above roughly 2000 degrees Celsius inside a graphite crucible and recondensed on a cooler seed crystal held at a controlled gradient above it. Published work grows 100 mm 4H-SiC at 2050 to 2150 degrees Celsius measured at the crucible top and pressures of 5 to 30 mbar, over runs measured in days rather than hours. That single difference — sublimation instead of melt pulling — reshapes the equipment, the consumables, the defect problem and the economics of scaling to larger diameters. India's first commercial SiC capacity is now under construction, which makes the equipment and materials layer a live sourcing question rather than a theoretical one.
Why SiC cannot be grown like silicon
Every intuition built on Czochralski silicon has to be set aside at the door. A CZ puller melts polysilicon in a quartz crucible and draws a growing crystal upward out of the liquid, and almost everything about the process — seeding, necking, body growth, taper, pull rate, crucible rotation — depends on there being a stable melt to pull from. Silicon carbide does not offer one under ordinary conditions. The route the industry actually uses is sublimation.
In physical vapour transport, SiC source material is heated inside a graphite crucible until it sublimes, the vaporised silicon- and carbon-bearing species travel through the gas phase along an imposed axial temperature gradient, and they recondense on a cooler seed crystal to build the boule layer by layer. Mersen, which supplies insulation for this process, describes the sequence plainly: source material heated above roughly 2000 degrees Celsius in a graphite crucible sublimes, and the vapour condenses onto a cooler seed. The crucible is not a container the way a quartz crucible is; it is the reaction vessel, the thermal shaper and, in induction-heated designs, part of the heating circuit.
The consequences follow directly. Growth is slow and boules are short compared with a silicon ingot, so a substrate line produces far fewer wafers per furnace-day. The process runs opaque — there is no visible meniscus to control against — so it is steered by thermal design and simulation rather than by watching the crystal. And the whole growth environment sits at temperatures where the hot zone itself becomes a consumable.
- SiC substrates are grown by sublimation and recondensation, not by pulling from a melt
- The graphite crucible is process equipment, not a passive container
- Runs are long and boules are short: throughput per furnace is structurally lower than CZ silicon
- Process control is thermal-field design, not real-time visual control of a growth interface
What the published growth window looks like
Public research gives a usable picture of the regime, and it is worth anchoring expectations to it rather than to vendor adjectives. A 2022 study in Materials by Steiner and Wellmann at FAU Erlangen-Nurnberg grew four 100 mm 4H-SiC crystals by PVT with growth temperatures between 2050 and 2150 degrees Celsius measured at the crucible top and pressures set between 5 and 30 mbar, on seeds oriented 4 degrees off-axis. A 2025 ACS Omega study of an eight-inch resistance furnace design reports growth above 2100 degrees Celsius at 1 to 10 mbar under an argon flow with a nitrogen dopant stream, across an experimental run of 120 hours.
Those numbers are the shape of the problem, not a recipe. The working point depends on crucible geometry, insulation package, source packing, seed diameter and target polytype, and it is established through qualification rather than transplanted between furnaces. What the literature does establish clearly is that the process is defect-limited rather than throughput-limited. The FAU study catalogues basal plane dislocations, threading edge and threading screw dislocations and stacking faults, and finds that stress induced by nitrogen doping — through its effect on the coefficient of thermal expansion — was orders of magnitude higher than stress from the seed mounting method. A doping decision made for electrical reasons propagates straight into the structural quality of the crystal.
This is why the review literature on sublimation growth spends its time on defect formation, interface morphology and in-situ observation. Wellmann's 2022 review in Materials Science Forum covers X-ray based imaging of the PVT process and continuum dislocation dynamics modelling to predict how dislocations form and move — an indication of where the difficulty genuinely sits.
- Anchor process expectations to published growth windows, then qualify your own
- Doping is not electrically isolated: it changes thermal expansion and therefore crystal stress
- Defect density, not growth rate, is the practical constraint on substrate value
- Expect simulation and in-situ observation to be part of process development, not optional extras
The hot zone and the consumable layer
At SiC growth temperatures the material set narrows sharply. Graphite does the structural work — crucible, lid, susceptor, seed holder, fixtures — and carbon insulation does the thermal work, and both are exposed to an aggressive silicon- and carbon-bearing vapour for the length of every run. Mersen markets ultra-purified graphite and insulation specifically for this duty, citing thermal capability up to 2400 degrees Celsius, contamination prevention, resistance to aggressive media and machinability into precise geometries. The insulation is not there only to save energy; it sets and holds the axial gradient that drives transport from source to seed, and a change in the insulation package is a change in the process.
Purity has to be specified the way it is specified for silicon hot zones — by the elements that matter, not by total ash. The same nominal ash content behaves very differently depending on whether it is boron, nitrogen-bearing residue or a transition metal, and in a wide bandgap substrate destined for high-voltage devices the electrically active impurities are the ones that decide whether the crystal is worth anything. Coatings, where used, add another qualification layer rather than removing one.
Heating method is a genuine architectural fork, and it becomes decisive with diameter. The 2025 ACS Omega work compares the two directly for eight-inch growth: an induction-heated configuration showed a radial temperature difference of 96.5 degrees Celsius and an axial difference of 270.6 degrees Celsius, while the proposed resistance-heated design reduced those to 12 and 41.9 degrees Celsius, with the authors attributing the induction limitation to electromagnetic skin effects at large diameter. The study reports an eight-inch ingot of more than 20 mm thickness with resistivity uniformity in a narrow band. Anyone specifying equipment with a 200 mm roadmap in mind should treat heating architecture as a first-order question rather than a vendor preference.
- Graphite and carbon insulation are process-defining consumables, not spares
- Specify purity by critical-element package for the intended device voltage class, not by total ash
- Insulation geometry sets the gradient: treat any change as a process change requiring re-qualification
- Heating architecture constrains achievable diameter — settle it before the equipment order
From boule to substrate, and why the back end is not free
A grown SiC boule is only the first half of a substrate. It still has to be oriented, cropped, sliced, lapped, polished and inspected, and SiC is one of the hardest materials in industrial use, which makes each of those steps slower, more consumable-hungry and more yield-sensitive than the silicon equivalent. Kerf loss matters disproportionately because the boule is short to begin with, which is why wire slicing, laser-assisted separation and thickness control get so much engineering attention in this segment.
The metrology that follows is different in kind from solar wafer inspection. Substrate acceptance turns on crystallographic quality — polytype uniformity, micropipe and dislocation density, resistivity uniformity, bow, warp, surface finish and subsurface damage — because everything downstream is an epitaxial layer grown on that surface. A substrate that passes a dimensional check and fails a defect check is not a lower grade of the same product; it is scrap for the device maker who buys it.
For a project team, the practical implication is that a SiC substrate plan is really three plans stacked together — growth, back-end processing and characterisation — and they have to be specified against one another. Choosing a growth architecture without settling how boules will be sliced and how substrates will be qualified is how programmes end up with crystals nobody will buy.
- Slicing, lapping and polishing SiC is a hard-materials problem, not a scaled silicon process
- Kerf and thickness control matter more when boules are short
- Acceptance is crystallographic: polytype, dislocations, resistivity uniformity, bow and warp, subsurface damage
- Specify growth, back end and metrology as one system, not three sequential purchases
Where India actually stands
The compound semiconductor layer of India's programme is no longer a proposal. The India Semiconductor Mission's public record shows units moving through approval and construction across several categories, including an integrated compound semiconductor fab and ATMP facility approved for Dholera in May 2026, alongside packaging units at Sanand, Surat, Bhubaneswar and Jewar at various stages from approval to commercial production. The direction of travel is toward wide bandgap and advanced packaging rather than leading-edge silicon logic, which is a reasonable read of where India's demand actually is.
On silicon carbide specifically, two efforts are visible. SiCSem, working with UK-based Clas-SiC, has an approved silicon carbide project at Bhubaneswar in Odisha, reported at an annual capacity of 60,000 wafers and 96 million devices, aimed at electric vehicles, defence, railways, fast charging and photovoltaic inverters. Separately, RIR Power Electronics announced approval and fiscal support from the Government of Odisha for a silicon carbide semiconductor plant at Bhubaneswar at an investment of 618 crore rupees, targeting automotive, renewable energy, industrial automation and power electronics. Project scope, phasing and timelines should be confirmed against each company's own current disclosures before being relied on commercially; announced capacity and installed capacity are different things, and in a first-of-its-kind facility the gap between them is usually measured in years.
The sourcing consequence is immediate even before those plants run. A SiC programme in India will import its growth furnaces, its ultra-pure graphite and carbon insulation, its slicing and polishing line and much of its metrology, and it will be qualifying suppliers in a market where the same materials vendors are simultaneously serving silicon crystal growth and a recovering global SiC device demand. Lead times on high-grade graphite and insulation have been long enough in recent years to sit on the critical path of a project schedule. That is a procurement and qualification problem, and it is best addressed at specification stage rather than after an equipment order is placed.
- India's compound semiconductor capacity is under construction, not hypothetical — but announced capacity is not installed capacity
- Verify project scope and timing against each company's own current disclosures
- Growth furnaces, graphite, insulation, slicing and metrology are all imported qualification decisions
- Put long-lead consumables on the project critical path from the specification stage
How JRST supports this requirement
JRST supports compound semiconductor and substrate projects on the parts that are decided before an order is placed: growth architecture and heating-method evaluation, hot zone and consumable specification, back-end processing scope, metrology and acceptance criteria, supplier identification and qualification across equipment and materials, and lead-time sequencing against the project schedule. Figures on this page are drawn from public research, vendor-published material and public programme records and should be validated for the specific project; announced project capacities are company or programme statements, not verified installed capacity. Final capability, warranty, performance and compliance commitments are defined against the customer's documented requirement.
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Mohammed Saif Zaveri connects JRST's industrial content to execution conversations.
As Co-Founder and designated partner of JRST Technology LLP, Mohammed Saif Zaveri works across industrial growth, strategic partnerships, client conversations, equipment strategy, and project pathways for silicon, solar, semiconductor, and advanced-manufacturing opportunities.
This knowledge page is part of JRST's public industrial knowledge base, designed to help buyers move from search terms and early research toward a structured technical-commercial discussion.
View Mohammed Saif Zaveri's profileConnect on LinkedInFrequently asked questions
Why is silicon carbide not grown by the Czochralski method?
Because there is no practical melt to pull from under ordinary conditions. Bulk SiC is instead grown by physical vapour transport: source material is sublimed inside a graphite crucible above roughly 2000 degrees Celsius and recondensed on a cooler seed crystal held at a controlled axial gradient. Everything that follows — slow growth, short boules, thermal rather than visual process control, a hot zone that is itself a consumable — comes from that difference.
What temperature and pressure does SiC PVT growth run at?
There is no universal setting, but the published regime is well documented. A 2022 Materials study grew 100 mm 4H-SiC at 2050 to 2150 degrees Celsius measured at the crucible top with pressure set between 5 and 30 mbar. A 2025 ACS Omega study of an eight-inch furnace reports growth above 2100 degrees Celsius at 1 to 10 mbar. The working point depends on crucible geometry, insulation, source packing, seed size and target polytype, and is established during qualification.
What limits SiC substrate quality?
Defects, not growth rate. The literature focuses on basal plane dislocations, threading edge and screw dislocations, stacking faults and polytype stability. Notably, a 2022 FAU study found that stress induced by nitrogen doping, through its effect on thermal expansion, was orders of magnitude higher than stress caused by the seed mounting method — meaning a doping choice made for electrical reasons directly affects structural quality.
Does induction or resistance heating matter for SiC growth?
It becomes decisive as diameter increases. A 2025 ACS Omega study comparing the two for eight-inch growth reports a radial temperature difference of 96.5 degrees Celsius and an axial difference of 270.6 degrees Celsius for an induction configuration, against 12 and 41.9 degrees Celsius for the proposed resistance-heated design, attributing the induction limitation to electromagnetic skin effects at large diameter. If a 200 mm roadmap exists, heating architecture should be settled before the equipment order.
What role does graphite play in a SiC furnace?
A structural and thermal one. Graphite forms the crucible, lid, seed holder and fixtures, and carbon insulation sets the axial gradient that drives transport from source to seed. Mersen, which supplies insulation for SiC PVT, cites capability up to 2400 degrees Celsius along with contamination prevention and resistance to aggressive media. Purity should be specified by critical-element package for the intended device voltage class rather than by total ash figures.
Where is silicon carbide capacity being built in India?
Principally in Odisha at present. SiCSem, with UK-based Clas-SiC, has an approved silicon carbide project at Bhubaneswar reported at 60,000 wafers and 96 million devices a year for EV, defence, rail, fast charging and PV inverter applications. RIR Power Electronics has announced approval and state fiscal support for a 618 crore rupee silicon carbide plant, also at Bhubaneswar. The India Semiconductor Mission's public record also shows an integrated compound semiconductor fab and ATMP facility approved for Dholera in May 2026. Scope and timing should be verified against current company disclosures.
How can JRST help on a silicon carbide substrate programme?
JRST works at the specification, sourcing and qualification layer: growth architecture and heating-method evaluation, hot zone and consumable specification including graphite grade and insulation package, back-end slicing and polishing line scope, metrology and acceptance criteria, supplier identification and qualification, and lead-time planning for long-lead consumables. Final capability, warranty and performance commitments are defined against the customer's documented requirement.
Primary sources and further reading
Last reviewed 2026-09-08. Technical scope, policy eligibility, availability, and commercial terms should be independently confirmed for each project.